In a dual damascene architecture, wiring patterns are etched into a dielectric, or insulating layer. See, e.g., Handbook of semiconductor interconnection technology, edited by Schwartz et al., Marcel Dekker 1998; and Copper-Fundamental Mechanisms for Microelectronic Applications, Murarka et al., Wiley 2000. The conductor material (typically copper) is then inlaid into those features. There are two types of features used for this purpose: trenches, which form the actual wiring template; and vias, which make connection to the metal level below. Creating such structures requires two passes through the photo-lithography process. Either the vias are formed first and then the trenches or vice versa.
The dielectric stack requirements for dual damascene include the primary insulating layer and a thin copper diffusion barrier or selective metal barrier. Additional layers may be included to facilitate fabrication, such as an intermediate etch stop, hard mask, etc.
An anti-reflective layer (or ARL) is often used for photolithographic processes. The ARL minimizes the total reflection of light from layers under the photoresist and the interface between the photoresist layer and the underlying layer. By adjusting the thickness, t, refractive index, n, and extinction coefficient, k, of the ARL film, as shown in FIG. 1, a destructive interference can be obtained in the photoresist with equivalent intensities of incident and reflective light. As a result, zero reflectivity can be reached under ideal conditions. Thus, an ARL improves the accuracy of pattern transfer when the photoresist is developed.
FIG. 2 shows a schematic diagram of a simplified lithography process flow of a via-first dual damascene process. Typically, anti-reflective layer 18 is deposited onto underlying layer 12, which is being patterned over a film stack. Underlying layer 12 is generally dielectric material deposited on a barrier layer 20. Photoresist 10 is then spun onto the top of the anti-reflective layer. See, FIG. 2 (a). The process proceeds through (b) via photoresist development to (c) via etch to the barrier layer 20 to (d) via photoresist removal and cleaning to (e) trench photoresist coating and (f) trench photoresist development. The exposed portion of the photoresist layer 10 is removed when photoresist layer 10 is developed, yielding the clean vertical walls shown in FIG. 2(b) when UV radiation is incident on area of the top surface of photoresist layer 10, exposing a portion of the photoresist layer 10. When developed, the trench should be patterned properly and yield a vertical wall, as shown in FIG. 2(f).
However, this identity in pattern after the development step is not always realized. More specifically, silicon dioxide (SiO2) historically has been used as the primary interconnect insulating layer. With device geometries shrinking and speeds increasing, the trend now is towards insulating materials with lower dielectric constants (low-k).
Substantially nitrogen-free (NF) ARLs have been developed to eliminate footing and inhibit the photoresist poisoning in damascene applications. The NF ARLs are compatible with chemically amplified photoresists found in lithography processes using DUV radiation and may be used with any wavelength of UV radiation.
However, current methods of processing wafers as described above may permit moisture to penetrate into the low-k dielectric. Moisture from the atmosphere and overlying layers may penetrate the low-k film during subsequent processing steps. The less dense low-k film, particularly the ultra low-k film, may absorb and keep the moisture easily in the film. The moisture then releases from the opened via during the etch process. Moisture release significantly effects plasma etch rate, especially in isolated vias. Moisture release may result in the via etch shown in FIG. 2(c) slowed down and not reaching the barrier layer 20 in the desired etch duration.
There is a need for improved methods of plasma etching of dual damascene features in low-k dielectric materials. It would be desirable to provide layers on the low-k dielectrics that have anti-reflective properties and limit the effect of moisture release on plasma etch.